1. Field of the Invention
The present invention relates to a data detection apparatus for detecting the data reproduced from a disk apparatus or the like. More particularly, the present invention relates to a phase lock loop for reproducing a clock component included in a signal reproduced from an optical disk medium on which information is digitally recorded so that the linear recording density becomes approximately constant.
2. Description of the Related Art
Recently, information is more actively and widely digitized in the information-related field as well as in the audio-video field. Attention is focused on an optical disk as a medium for digitally recording audio information, video information or the like. The optical disk has excellent properties such as random access ability, medium exchangeability, capability of accommodating information and the like as compared with other medium such as other magnetic tapes or disks. As a method for recording the maximum information on such an optical disk, a constant linear velocity (CLV) recording method is used. According to the CLV recording method, the maximum recording capacity is realized within the same disk size by unifying and maximizing the bit recording density throughout a recordable region of the recording medium. In the case where the data recorded by the CLV recording method is to be reproduced, it is normally necessary to vary the rate of disk revolutions in accordance with a radius of a region to be reproduced, that is, a radius of a track so as to keep a reproduced data rate constant. The reproduced data rate is set to be a predetermined data rate by providing a phase lock loop for a clock component included in a reproduced signal so as to convert the reproduced signal into digital data and further providing a frequency loop for controlling a motor, which serves to lock the thus obtained clock frequency with a fixed frequency.
Since a capture range of the phase lock loop used for converting a reproduced signal into the digital data is normally small, that is, within the range of .+-.5%, it is necessary to control the number of revolutions with high precision in accordance with the radius of the track for performing a lock-in operation. However, since it is not easy to control the number of revolutions with high precision, it is difficult to establish the lock-in. As an example of a reproduced signal, when information is subjected to a digital modulation satisfying the (d, k) rule as used in a compact disk (in the case of a compact disk, d-2, k=10), and then is subjected to a Non Return to Zero, Inverse (NRZI) modulation, and is recorded in a Pit Width Modulation (PWM) in which the number of consecutive codes "1" and the positions thereof correspond to a pit length and a pit position, the data is reproduced based on a rising edge and a falling edge of the reproduced signal. By utilizing that these edges can be obtained at discrete time intervals determined by the (d, k) rule, clock information of the reproduced data is reproduced by using a phase lock loop.
A conventional data detection apparatus will be described with reference to FIG. 19. The data detection apparatus includes: an optical disk 18; a disk motor 19 for rotating the optical disk 18; an optical pick-up 20 for reproducing the information recorded on the optical disk 18; a digitizing section 1 for digitizing a reproduced signal at a predetermined voltage level so as to output a digital signal; an oscillator 5 for outputting a clock signal having a frequency proportional to a voltage output from a low pass filter 4; a phase comparing section 2 for comparing the phases between the digital signal and the clock signal so as to output a phase difference signal; a charge pump section 3 for discharging or absorbing a current in accordance with the phase difference signal; a low pass filter 4 for converting a current output from the charge pump section 3 into a voltage while limiting a frequency band thereof so as to input the obtained voltage to the oscillator; and a motor controller 21 for controlling the motor rotations.
The operation of the thus configured data detection apparatus will be described with reference to FIG. 20. A signal (a) reproduced from the optical disk 18 is digitized at a predetermined voltage level in the digitizing section 1 to be converted into a digital signal (b). The oscillator 5 has characteristics of oscillating a clock signal having a frequency proportional to an input voltage, for example, as shown in FIG. 21, and oscillates at a free-run frequency (c) prior to a lock-in. The phase comparing section 2 compares the phase of a digital signal and the phase of an oscillating clock signal. The phase comparing section 2 outputs a positive pulse (f) or a negative pulse (g) in accordance with the relation of the phases of the two inputs as shown in FIG. 22. More specifically, a positive pulse (f) is output in the case where the phase of the clock signal is ahead of that of the digital signal and a negative pulse (g) is output in the case where the phase of the digital signal is ahead of that of the clock signal, at time intervals in accordance with the phase difference. The charge pump section 3 outputs a positive or negative current in accordance with the amount of the phase difference. The charge pump section 3 includes current sources I1 and I2 and switches S1 and S2, for example, as shown in FIG. 23. The current source I1 allows a predetermined current to flow by rendering the switch S1 conductive with a negative pulse; while the current source I2 absorbs a predetermined current by rendering the switch S2 conductive with a positive pulse. The low pass filter 4 comprises a resistance R and a capacitance C, for example, as shown in FIG. 24. The low pass filter 4 converts a current output from the charge pump section 3 to a voltage while limiting a frequency band of the current. The oscillator 5 generates a clock signal having a frequency proportional to a voltage generated by the low pass filter 4. In this manner, in the case where the phase of the clock of the oscillator 5 is ahead of that of the digital signal, a positive pulse is output from the phase comparing section 2 to allow the charge pump section 3 to absorb the current. As a result, a filter voltage drops to lower the clock frequency output from the oscillator 5, thereby delaying the clock signal in terms of phase. On the other hand, in the case where the phase of the clock of the oscillator 5 is behind that of the digital signal, a negative pulse is output from the phase comparing section 2 to allow the current to flow from the charge pump section 3. As a result, a filter voltage boosts the clock frequency output from the oscillator 5, thereby advancing the clock signal in terms of phase. As described above, a negative feedback control functions so as to make the frequencies of the clock and the digital signal almost identical to each other. At last, the widths of a negative pulse and a positive pulse become respectively small to perform a phase lock-in of the digital signal (b) and the clock signal (d). Furthermore, in the case where the data is reproduced at a fixed transfer rate by performing the CLV control, the rotation of the motor is controlled so that an oscillation frequency obtained in the oscillator 5 of a phase-locked loop is used as a fixed frequency.
However, since the edge information of the digital signal is modulated in accordance with the recorded data, the edge information does not uniformly appear. Therefore, a pseudo lock of the phase lock loop occurs at a frequency other than a predetermined frequency. In order to avoid the pseudo lock, it is necessary to adjust the rotation of the motor so that a reproduced signal rate is almost equal to a predetermined rate.
The small range of the lock-in of a phase lock loop results from the following fact. The input data is subjected to pulse modulation, and is therefor discontinuous in terms of time. Thus, the lock-in can be performed only in terms of phase but not in terms of frequency.
In this way, the lock-in of a phase lock loop may be improved, and an apparatus which does not cause a pseudo lock is needed. Thus, a lock-in circuit requires the motor controller 21 to adjust the rotation of the motor so that a reproduced signal rate is almost within the capture range as shown in FIG. 25. For example, the shortest or longest pulse width of a reproduced signal is obtained by utilizing a rising edge and a falling edge of the reproduced signal (a), which can be obtained at discrete time intervals determined by the (d, k) rule as shown in FIG. 26. The motor controller 21 requires a circuit for controlling the rotation of the motor so that the obtained pulse width is set to a predetermined value. Since the disk rotates at high speed in the case where a pulse width is shorter than a predetermined width as represented by a pulse width (h), the rotation speed is decreased. Since the disk rotates at low speed in the case where a pulse width is longer than a predetermined width as represented by a pulse width (i), the rotation speed is increased. In this manner, the motor speed is controlled so that a reproduced signal rate is within a capture range.
With the above configuration, however, the response speed of the motor is low. Therefore, it takes much time to adjust the disk rotation so as to be within the capture range, and such time occupies a large part of seek time.
Although it might be possible to shorten the adjustment time until a steady-state rotation of the motor is obtained, there is a limitation in a motor torque and a driving current. Moreover, in the case where the motor rotation is controlled by detecting the shortest pulse width or the longest pulse width of a reproduced signal, it is necessary to preserve a detection sampling period for a predetermined time or longer because the frequency of appearances of the shortest or longest pulse with is restricted. Thus, it is difficult to increase the frequency band.